20 beste Stellen als lead engineer in zürich zh – aktuell auf Personalsuche

Lead Custom Design Engineer
Synthara AG —Zürich, ZH
- Doktorat
- Master
- Mentoring
Lead KMP Software Engineer
Specialized —Cham, ZG
- 100%
- Mentoring
- Führungserfahrung
- Kommunikationsfähigkeit
Lead System Engineer 80%-100%
Prime21 AG —Zürich, ZH
- Teilzeit
- Englisch
- Windows
- Erfahrung in der IT
- Kostenloser Parkplatz
- Pensionskasse
Numerical Modeling Engineer
Proxima Fusion —Zürich, ZH
- 100%
- Doktorat
- Master
- C++
Lead Security Engineer, Detection & Response
Snapchat —Zürich, ZH
- 100%
- Hybrides Arbeiten
- Doktorat
- Windows
- Master
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R&D Test Engineer Instrumentation (m/f/d), (80-100%)
Accelleron —Baden, AG
- CAD
- Englisch
- Master
- Eltern-/Erziehungsurlaub
Process Engineer
SR Technics —Zürich, ZH
- 100%
- Englisch
- Master
- Bachelor
5 Tage
Lead System Engineer (Linux, Network)
Ergon Informatik AG —Zürich, ZH
- CHF 100’000 - CHF 140’000 pro Jahr
- 100%
- Hybrides Arbeiten
- Englisch
- Linux
Direkt bewerben
Lead Digital Signal Processing Engineer
Destinus —Zürich, ZH
- Hybrides Arbeiten
- Doktorat
- Master
- Analysefähigkeit
Direkt bewerben
Lead Machine Learning Engineer & Lead Systems AI Engineer
ETH Zürich —Zürich, ZH
- Teilzeit
- Doktorat
- Englisch
- Forschungserfahrung
5 Tage
System Engineer Operations (80-100%)
iSource AG —Glattbrugg, ZH
- Englisch
- Erfahrung in der IT
Lead Database Architect (80-100%)
TWINT —Zürich, ZH
- Hybrides Arbeiten
- Oracle
- Englisch
- Bachelor
- Homeoffice-Möglichkeit
- Eltern-/Erziehungsurlaub
Practice Lead - Google Workspace Migrations and Enablement
EPAM Systems, Inc. —Zürich, ZH
- Management-Erfahrung
- Führungserfahrung
- Kommunikationsfähigkeit
- Eltern-/Erziehungsurlaub
- Pensionskasse
Team Lead - Data Architecture
Sika —Zürich, ZH
- 100%
- Erfahrung in der IT
- Führungserfahrung
- Kommunikationsfähigkeit
Lead .NET Software Engineer (a)
ERNI —Zürich, ZH
- Hybrides Arbeiten
- Englisch
- Softwareentwicklung
Configuration Management Engineer (m/f/d)
Consulteer —Zürich, ZH
- 100%
- Hybrides Arbeiten
- Management-Erfahrung
- Englisch
- Analysefähigkeit
Direkt bewerben
9 Tage
Lead Engineer - Civil
Kanadevia Inova —Zürich, ZH
- 100%
- Hybrides Arbeiten
- Englisch
- Master
- Bachelor
Direkt bewerben
2 Tage
Engineering Manager, Guard Foundations (Zürich)
Lakera —Zürich, ZH
- 100%
- Hybrides Arbeiten
Member of the technical staff (Software Engineer)
Jua —Zürich, ZH
- CHF 125’000 - CHF 160’000 pro Jahr
- 100%
- Hybrides Arbeiten
- Microsoft Excel
- AWS
- Bachelor
GT/ST/GEN Accessories Instrumentation Design Lead Engineer (m/f/d)
GE Vernova —Baden, AG
- 100%
- Systemdesign
- Führungserfahrung
- Kommunikationsfähigkeit

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Lead Custom Design Engineer

Synthara AG
Zürich, ZH

Jetzt bewerben

Details zur Stelle

Qualifikationen

Doktorat
Master
Mentoring
Führungserfahrung
Python

Vollständige Stellenbeschreibung

Role

Location: Zürich, Switzerland
Seniority: 7+ years (custom digital, analog, or memory), team leadership

Lead the development of high-performance, custom based digital compute or SRAM memory designs to power our compute-in-memory SRAM (ComputeRAM®). You will own architecture, circuit design, verification, and silicon correlation for advanced nodes down to 5 nm and below, and you will lead a small team of custom designers and layout engineers to predictable, production-grade outcomes. Expect hands-on work on bitcell-adjacent periphery, datapath interfaces, optimizing data movement, as well as tight collaboration with full-custom layout, digital, backend, DFT, and test.

What you’ll do

Own the product roadmap: define specs, PPA targets, verification depth, and quality bars for new SRAM variants and CxR-adjacent custom blocks.
Design & verify memory or datapath subsystems, including sense amps, data drivers, multipliers, adders, register files, timing/control FSMs, etc..
Engineer for advanced nodes: close on variation (corners, Monte-Carlo), stability, noise/IR drop, device reliability, and wake-up/low-power behaviors in FinFET and FDSOI.
Integrate for product: define clean digital boundaries (standard-cell and bus interfaces), latency/handshake contracts, and timing budgets so blocks drop into a digital-on-top mixed-signal flow.
Silicon correlation: plan bring-up, build characterization benches, analyze ATE data, and publish correlation and errata with clear fixes.
Redundancy & test: specify and validate redundancy/repair schemes; work with DFT (MBIST and Scan) test coverage; sign off on a production test plan.
Partner with layout: co-plan floorplans, matching/guarding, shielding, and routing topologies; review extraction and fix EM/IR issues early.
Elevate method & team: coach designers, run reviews, enforce checklists, and grow automation (Python/Tcl) for regressions, reporting, and collateral generation.

Outcomes (first 18 months)

Tape-in and silicon of at least one production-grade CxR custom memory block meeting spec across PVT, with signed correlation and test reports.
A reusable design kit (models, constraints, verification plans, char scripts, checklists) that shortens the following variant’s cycle time.
A high-functioning custom team with clear ownership (periphery, timing/control, modeling, characterization) and reliable delivery metrics.
Quantified PPA and yield gains from design or methodology improvements you led.

Requirements

MS or PhD in Electrical/Computer Engineering (or similar) and 7+ years in custom digital, memory, or analog design.
Track record of end-to-end ownership of production-grade functional blocks, including sign-off and silicon correlation.
Deep understanding of high-performance and low-power circuit design on FinFET nodes (stability, variation, leakage, performance).
Experience leading a small team (mentoring, reviews, planning) and coordinating tightly with layout, digital, backend, DFT, and test.
Clear communication, structured documentation, and a quality-first mindset.

Nice to have

Scripting for design and characterization automation (Python, Tcl) and model/report generation.
Experience with memory compilers, characterization flows, and verification environments.
DTCO/STCO exposure to align device, bitcell, and periphery choices with product goals.
Background with production test strategies.
Familiarity with compute-in-memory constraints and with integrating custom memory into large digital systems.

Apply

Send your CV and a short note (2–3 paragraphs on a design you owned, your toughest bug & how you solved it, an intro on what you like to do and how you see yourself as an engineer)

Interview flow (indicative)

30-min intro with HR (role/context)

First Technical deep dive

Second Technical Deep Dive

(Optional) Third Technical Deep Dive

Systems/product conversation with management

Jetzt bewerben

Erweiterte Suche

lead engineer Jobs in zürich zh

Lead Custom Design Engineer

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R&D Test Engineer Instrumentation (m/f/d), (80-100%)

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Practice Lead - Google Workspace Migrations and Enablement

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Configuration Management Engineer (m/f/d)

Lead Engineer - Civil

Engineering Manager, Guard Foundations (Zürich)

Member of the technical staff (Software Engineer)

GT/ST/GEN Accessories Instrumentation Design Lead Engineer (m/f/d)

Ich möchte aktuelle Job-E-Mails für Stellen als lead engineer in zürich zh erhalten

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