10 beste Stellen als simulation engineer in zürich zh – aktuell auf Personalsuche

Technical Lead – Physical Design (RTL to GDSII)
Synthara AG —Zürich, ZH
- Python
Senior Electrical Engineer
Oxford Instruments plc —Zürich, ZH
- Englisch
- Master
- Kommunikationsfähigkeit
Software Engineer: Infra Focus [100%] Zurich Hybrid
Optiml —Zürich, ZH
- Überstunden
- Hybrides Arbeiten
- Informatik
- Englisch
- Master
Direkt bewerben
Senior Game Developer
Gravis Robotics —Zürich, ZH
- 100%
- Englisch
- Master
- C++
Staff Analog Design Engineer (f/m/d)
Renesas Electronics —Zürich, ZH
- 100%
- Homeoffice
- Doktorat
- Laborerfahrung
- Master
Direkt bewerben
Internship - Humanoid Motion Generation (Diffusion or Flow Matching)
Flexion Robotics —Zürich, ZH
- Doktorat
- Master
- Softwareentwicklung
Direkt bewerben
PostDocs and/or Senior Engineers in Electromagnetics
IT'IS Foundation —Zürich, ZH
- Doktorat
- Englisch
- C++
Risk Analytics - Atlas Axais
deCircle —Zürich, ZH
- 100%
- Homeoffice
- Microsoft Excel
- Management-Erfahrung
- SQL
Direkt bewerben
Senior Maschinenbauingenieur:in elektrischer Antriebsstrang
Flux Mobility —Winterthur, ZH
- 100%
- Mechanikkenntnisse
Reinforcement Learning Expert - Humanoid (human)
Neura Robotics —Zürich, ZH
- 100%
- Informatik
- Doktorat
- Englisch
Direkt bewerben

More jobs to discover

Find similar jobs that you might be interested in.

OFCI Lead
Mercury Engineering —Zürich, ZH
Bei Mercury ist es unsere Pflicht, unsere Mitarbeiter zu ermutigen und zu unterstützen, damit sie ihre Vision von sich selbst verwirklichen können.
16 Std.

Ich möchte aktuelle Job-E-Mails für Stellen als simulation engineer in zürich zh erhalten

Wenn Sie sich bei Ihrem Konto anmelden, stimmen Sie den Nutzungsbedingungen, den Richtlinien zur Verwendung von Cookies sowie der Datenschutzerklärung von SimplyHired zu.

Weitere Job-Standorte erkunden

simulation engineer jobs near zürich zh

Jobs als Staff Engineer in Zürich, ZH

Jobs als Ingenieur Maschinenbau in Winterthur, ZH

Jobs als Senior Electrical Engineer in Zürich, ZH

Jobs als Senior Engineer in Zürich, ZH

Jobs als C# Net Developer, Banking, Contract To Permanent Zürich Singapore in Schlieren, Zh

Jobs als Senior Net Developer in Zürich, Zh

Jobs als Senior Scientist in Basel, Bs

Jobs als Staff Engineer in Genève, Ge

Jobs als Staff Engineer in Genf, Ge

Jobs als Engineer in Liechtenstein

Jobs als Staff Engineer in Kanton Zürich

Jobs als Level Designer in Genf, Ge

Jobs als Industrial Designer in Zürich, Zh

Jobs als Designer in Remote

Jobs als Ingenieur Maschinenbau in Flughafen Zürich, Zh

Jobs als Ingenieur Student in Zürich, Zh

Jobs als Ingenieur Maschinenbau in Sursee, Lu

Jobs als Ingenieur in Schaffhausen, Sh

Jobs als Risk Engineer in Zürich, Zh

Jobs als Software Engineer in Lausanne, Vd

Technical Lead – Physical Design (RTL to GDSII)

Synthara AG
Zürich, ZH

Jetzt bewerben

Details zur Stelle

Qualifikationen

Git
Python

Vollständige Stellenbeschreibung

Role

Location: Zürich, Switzerland
Seniority: 10+ years (ASIC implementation; 2+ tapeouts as owner)

Own the end-to-end RTL-to-GDSII implementation for complex IP/SoC subsystems and build the backend team that scales it. You’ll define the methodology, constraints, and quality metrics that the team shall adhere to. The team you lead will be responsible for synthesis, floor planning, P&R, clock tree synthesis, multi-corner STA, design for testability, and ECOs to achieve sign-off. You and your team will collaborate tightly not only with our RTL/digital team but also with our full-custom and full-custom layout team, integrating our full-custom design blocks into a digital-on-top mixed ASIC design. This is a hands-on technical leadership role, where you will not only set the flow and lead the team, but also personally de-risk and own the most challenging aspects of the design.

What you’ll do

Methodology: Define and maintain a modern RTL-to-GDS flow, including constraint strategy, libraries/PDKs, UPF/CPF, and sign-off checks.
Implementation: Run synthesis, floorplan, partitioning, P&R, CTS, routing, extraction, and closure.
PPA & quality: Create predictable PPA targets and tracking, lead timing/power ECOs; correlate pre/post-layout timing
Integration: Integrate custom macros, SRAMs, and I/O, manage clocking strategy, CDC, and hierarchical/hard-macro integration with LEF.
Low power: Own power intent (UPF/CPF), isolation/retention strategies, level shifting, and power-aware STA/simulation.
DFT & test hooks: Partner with DFT on scan/MBIST insertion and test timing; ensure routes and constraints don’t compromise test coverage or bring-up.
Automation & CI: Industrialize the flow with Tcl/Python automation, reproducible configurations, metrics dashboards, and CI/CD for nightly builds and regression testing.
Team: Recruit and performance-develop a 5+ engineer group, set sign-off standards, and ideally establish a flow-based build ensuring repeatability.
Foundry interface: Engage with foundries on PDK updates, waiver handling, antenna/density rules, and reliability guidance; maintain the flow of information.

Outcomes (first 18 months)

Tapeout of one or more blocks/subsystems with MCMM (Multi Corner Multi Mode) timing, closed, clean DRC/LVS, and signed-off IR/EM.
A documented, automated PD flow adopted across projects, with measurable cycle-time and PPA improvements.
A staffed and functioning backend team with clear ownership areas (timing, power/IR, integration, sign-off) and reliable execution metrics.
Golden constraints and library strategy (views, corners, derates) with proven correlation (synth – P&R – sign-off) and predictable ECO closure.

Requirements

10+ years in ASIC physical design; 2+ successful tapeouts as block/subsystem owner from synthesis to sign-off.
Deep expertise in one complete tool chain (Synopsys or Cadence)
Hands-on experience in power-optimization techniques, including glitch reduction and activity-based power correlation (VCD/SAIF).
Strong MCMM STA and timing-closure experience
Experience with grid planning, IR/EM analysis, and fixes. Proven floorplanning/partitioning and hierarchical integration (hard-macros, abstracts/LEF, feedthroughs, blockage strategy).
UPF/CPF know-how for multi-voltage, power-gated designs, including isolation/retention and power-aware STA and sim.
Scripting for automation (Tcl, Python) and version control (Git, Perforce, or similar)
Ability to work and lead the activities independently and assume responsibility for major decisions

Nice to have

DFT exposure (scan planning, test timing, MBIST integration) and formal equivalence workflows.
Package/board co-design awareness (bump/rail planning, SSO/PI, thermal assumptions).
7 nm FinFET) with multi-patterning/EUV constraints and variability considerations.
Familiarity with sign-off for safety-/quality-critical markets (automotive-style reliability targets, waiver governance, documentation rigor).

Apply

Send your CV and a short note (2–3 paragraphs on a design you owned, your toughest bug & how you solved it, an intro on what you like to do and how you see yourself as an engineer)

Interview flow (indicative)

30-min intro with HR (role/context)

First Technical deep dive

Second Technical Deep Dive

(Optional) Third Technical Deep Dive

Systems/product conversation with management

Jetzt bewerben

Erweiterte Suche

simulation engineer Jobs in zürich zh

Technical Lead – Physical Design (RTL to GDSII)

Senior Electrical Engineer

Software Engineer: Infra Focus [100%] Zurich Hybrid

Senior Game Developer

Staff Analog Design Engineer (f/m/d)

Internship - Humanoid Motion Generation (Diffusion or Flow Matching)

PostDocs and/or Senior Engineers in Electromagnetics

Risk Analytics - Atlas Axais

Senior Maschinenbauingenieur:in elektrischer Antriebsstrang

Reinforcement Learning Expert - Humanoid (human)

More jobs to discover

Ich möchte aktuelle Job-E-Mails für Stellen als simulation engineer in zürich zh erhalten

Related Searches

Weitere Job-Standorte erkunden

Role

What you’ll do

Outcomes (first 18 months)

Requirements

Nice to have

Apply

Interview flow (indicative)

Tools für Jobsuchende

Arbeitgebertools

Durchsuchen

Bleiben Sie in Kontakt