12 beste Stellen als python in district de lenzbourg ag – aktuell auf Personalsuche

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Senior Layout Engineer

Synthara AG
Zürich, ZH

Jetzt bewerben

Details zur Stelle

Qualifikationen

Python

Vollständige Stellenbeschreibung

Role

Location: Zürich, Switzerland
Seniority: 5+ years (custom analog/SRAM/custom-digital layout)

Own transistor-level and block-level custom layout for mixed-signal, SRAM, and custom-digital IP that powers our compute-in-memory SRAM (ComputeRAM®). You will plan floorplans, implement device-level layouts with production-grade matching/guarding, close DRC/LVS/PEX on advanced nodes down to 4 nm and below, and collaborate tightly with custom-design, digital, and PD/STA teams to hit aggressive PPA, yield, and reliability targets. You will bridge classic analog techniques (common-centroid/interdigitation, shielding, isolation) with FinFET/FDSOI rules, multi-patterning/EUV constraints, and modern DFM practices.

What you’ll do

Plan & implement full-custom layouts for standard cells, custom datapaths, and SRAM periphery/arrays.
Drive and provide feedback to the design team to converge on the most power-aware design layout possible.
Interface & integrate: align with schematic owners on constraints; define pins/abstracts, LEF views, keep-outs, and tiling for memory-like macros; coordinate with MBIST/scan wrappers and test hooks.
Automate & document: maintain checklists, templates, and layout guidelines; script repetitive tasks (TCL, Python)

Outcomes (first 18 months)

Tape-in and silicon of one or more custom blocks or macros with clean DRC/LVS/PEX and correlated post-silicon parasitics (report + lessons-learned).

Requirements

5+ years in custom layout for analog/SRAM/custom-digital IP; strong ownership from floorplan to sign-off.
Demonstrated quality on sub-28 nm nodes; practical know-how for FinFET/FDSOI, multi-patterning/EUV constraints, coloring.
Solid analog layout techniques: common-centroid, interdigitation, current-mirror symmetry, matched routing, shielding/guard rings, substrate noise isolation.
Working grasp of timing/IR/EM implications of layout; ability to read extraction/timing reports and iterate with designers/PD/STA.
Clear communication, rigorous documentation, and a collaboration mindset across custom design, digital, and backend teams.

Nice to have

Experience with SRAM arrays/periphery, redundancy/repair hooks, MBIST/scan routing constraints.
TCL/Python for layout automation and report generation.
DFM/DFY exposure
ESD/latch-up design practice; EM/IR sign-off collaboration at the macro level.
Comfort producing LEF and working with integration/floorplanning teams on macro delivery.

Apply

Send your CV and a short note (2–3 paragraphs on a design you owned, your toughest bug & how you solved it, an intro on what you like to do and how you see yourself as an engineer)

Interview flow (indicative)

30-min intro with HR (role/context)

First Technical deep dive

Second Technical Deep Dive

(Optional) Third Technical Deep Dive

Systems/product conversation with management

Jetzt bewerben

Erweiterte Suche

python Jobs in district de lenzbourg ag

Senior Layout Engineer

Machine Learning Engineer (Applied ML, B2B SaaS)

Senior Custom Design Engineer

Technical Lead – Physical Design (RTL to GDSII)

Senior Test Manager & Quality Engineer 100% (f/m/d)

Teamleiter Finishing (Schwerpunkt Auswuchten) (m/f/d, 80%-100%)

Citrix NetScaler Engineer 100% (f/m/d)

100 % (M/W/D) Junior Software Engineer im Cross-Company-Programm

Data Architect mit einem Flair für AI

(Senior) Software Systems Engineer Web Security

Senior Technical Consultant Omada/IGA (m/f/d)

Senior Java Engineer – HPC Cluster Development & Maintenance, 100% (f/m/d)

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